In the art of digital electronics, complete logic circuits are resident on a single circuit card. The circuit card includes the connective circuitry necessary to insert the circuit card into a digital subsystem. This design permits convenient replacement of the circuit card upon its failure by a new circuit card. Automatic diagnostic testing is employed on a regular basis to verify the satisfactory operation of each subsystem within a main system and to isolate the failure of the particular circuit card within the subsystem. On many system designs, such as flight simulator systems, the automatic diagnostic testing is conducted prior to utilizing the flight simulator system for training by performing a morning readiness test. A major problem that existed in the prior art was that the automatic diagnostic test was time consuming. Each circuit node of each circuit card within each subsystem must be validated by comparison data located within the software programming of a diagnostic computer. Each session of diagnostic testing consumed as much as thirty minutes of computer time.
Typically, logic circuit cards are interconnected and the data flows from one circuit card to another. Each circuit card is equipped with a diagnostic tap to interrupt the normal data flow and intercept data for testing that is resident within the circuit card. The test data is comprised of binary words which contain sixteen bits of binary data and the number of the words to be tested will vary depending upon the subsystem and circuit card to be tested. The prior art included circuit cards containing two thousand and forty-eight words per circuit card that were required to be verified as accurate. The process of verification included comparing each of the two thousand and forty-eight words of test data from each circuit card with a table of accurate values which included two thousand and forty-eight words of valid comparison data for each circuit card stored in the software of the diagnostic computer. Interposed between the diagnostic tap of the circuit card under test and the diagnostic computer was a diagnostic holding register. The diagnostic holding register was a sixteen bit register that was connected to the diagnostic tap of the circuit card under test. Each of the two thousand and forty-eight words was serially transmitted to the diagnostic holding register which transmitted an interrupt signal to the diagnostic computer. A central processing unit of the diagnostic computer received the interrupt signal indicating that test data was available. The central processing unit accepted the test data only after a delay including the time to process the interrupt signal and accept each word. Two thousand and forty-eight time delays were incurred for each circuit card in addition to the time for data comparison. Thus, the purpose of the diagnostic holding register was to hold each sixteen bit word from the circuit card under test until the time delay passed and the central processing unit was prepared to accept transmission of the sixteen bit word. The summation of the time delays created a rate of speed problem which was the major contributor to the time consumption problem. Utilizing a faster diagnostic computer would be financially prohibitive and thus the time consumption problem of the prior art remained unsolved.